About Me:

I’m a Master’s student in Electrical and Computer Engineering at Georgia Tech, specializing in computer architecture, GPU systems, and RTL/ASIC design. I enjoy working at the boundary between microarchitecture and implementation, turning architectural ideas into production-quality hardware.

Previously, I worked as an ASIC Engineer at Cisco, owning blocks in a SmartNIC network packet-parsing pipeline, and as a Wi-Fi MAC Design Intern at Qualcomm, where I implemented architectural optimizations that reduced block-level area by ~18%. My academic and research work spans GPGPU architecture (Vortex), FPGA prototyping, AXI/MMIO system design, and a TSMC 65 nm tapeout from RTL to post-silicon validation.